Verifying Hardware with Verb

Verb is a simulation-based functional verification framework for digital hardware designs.

Verb leverages file I/O and software programming languages to simulate hardware designs in their native hardware description language.

Verifying hardware with Verb is separated into 3 steps:

1. Model the hardware design in software to generate input vectors and expected output vectors

2. Simulate the hardware design by sending input vectors to the design under test, receiving output vectors from the design under test, and logging comparisons between simulated output vectors and expected output vectors

3. Analyze the logged comparisons for any errors

Sections

The following documentation will be mainly divided into 4 sections:

1. Tutorials - Step-by-step lessons using Verb
2. User Guide - General procedures for "how-to" solve common problems
3. Topic Guide - Explanations that clarify and provide more detail to particular topics
4. Reference - Technical information

About the Project

The project is open-source under the MIT license and is available on GitHub.

About the Documentation

Documentation system and methodology is inspired by Divio.