Converting Code

This page walks through the general procedure for transforming an already existing HDL project into a usable block within legoHDL.

Local projects

Determine the local path of your current workspace.

$ legohdl list -workspace

Move the HDL project's root folder within the current workspace's local path.
Open a terminal at the HDL project's root folder.
Initialize a block and provide its identifier, <block>.

$ legohdl init <block>

Remote projects

Copy the remote repository URL (paste it where <url> is in the following command).
From the terminal run, create a new block and provide its identifier, <block>.
- Add the -fork flag to detach the block from the remote repository url if you will not be able to push changes to it.
- Add the -open flag to optionally open the block in your configured text-editor.

$ legohdl new <block> -remote="<url>"

Off-The-Shelf Examples

This section lists random or popular HDL git repositories available on GitHub that are easily integrated into legoHDL.

Basic RISC-V CPU

Project: https://github.com/Domipheus/RPU.git
Author: Colin Riley

One-line command:

$ legohdl new cpu.riscv -remote="https://github.com/Domipheus/RPU.git" -fork -open

From the project's root directory:

$ legohdl info -more
--- METADATA ---
[block]
name     = riscv
library  = cpu
version  = 0.0.0
remote   = 
vendor   = 
requires = ()

--- STATS ---
Location = /Users/chase/develop/eel4712c/cpu/riscv/
Size     = 465.19 KB
Level    = DNLD
Required by:
        N/A

VHDL units:
    tb_unit_decoder_RV32_01    alu_int32_div_tb           
    tb_unit_alu_RV32I_01       rpu_core_tb                
    register_set               constants                  
    core                       alu_RV32I                  
    mem_controller             control_unit               
    decoder_RV32               alu_int32_div              
    lint_unit                  csr_unit                   
    pc_unit

Viewing the entity design hierarchy:

$ legohdl graph
INFO:   Identified top-level unit: core
INFO:   Identified top-level testbench: rpu_core_tb
INFO:   Generating dependency tree...
--- DEPENDENCY TREE ---
\- cpu.rpu_core_tb 
   \- cpu.core 
      +- cpu.mem_controller 
      +- cpu.pc_unit 
      +- cpu.control_unit 
      +- cpu.decoder_RV32 
      +- cpu.alu_RV32I 
      |  \- cpu.alu_int32_div 
      +- cpu.register_set 
      +- cpu.csr_unit 
      \- cpu.lint_unit 


--- BLOCK ORDER ---
[1]^-   cpu.riscv(@v0.0.0)

Everything checks out; from here you can release this block as a new version using release and reuse any designs in a different project.

Simple UART

Project: https://github.com/jakubcabal/uart-for-fpga
Author: Jakub Cabal